Variability aware gate delay model considering MIS for ultra-low power/energy CMOS circuits

Power is increasingly the primary design constraint for chip designers and one of the main techniques for addressing this concern is aggressive voltage scaling. Device variability increases with voltage scaling and significantly affects gate delays at low voltages. Although existing delay models for nearand sub-threshold circuits captures the effects of variability on gate delays, they do not capture advanced delay phenomenon such as multiple input switching (MIS; also known as near-simultaneous transitions) at inputs of a gate. As a result, most existing gate delay models often grossly underestimate worst case delays. In this paper we present a general approach for extending any delay model (pin-to-pin and beyond) to ensure that all minimum and maximum delay values computed are guaranteed to bound the corresponding delay values in silicon. We present extensive experimental results to demonstrate that MIS has significant impact (around 30-40%) on delays of nearand sub-threshold nominal gates. We develop our model empirically and show that it has practical run-time complexity and works equally well for super-, nearand sub-threshold circuits. In particular, via extensive experimentations we show that our model never underestimates the delay and tightly bounds the actual delays. (In contrast, in many of these experiments, existing delay models underestimate delays and always provide much looser bounds.)